Wideband Modulation in a Phase-Locked Loop Using an Additional Feedback Around the VCO (PhD viva voce)

Abstract: The thesis investigates bandwidth improvement techniques for phase-locked loops (PLL). Frequency modulation using the conventional PLL has a low modulation bandwidth, typically 10 to 100 times smaller than the reference frequency. High-frequency modulation can be achieved by either passing the modulating signal through a pre-emphasis filter or by additionally injecting the modulating signal at the input of the VCO. Both these methods are quite sensitive to the loop parameters and can vary widely across the process and temperature. This work proposes a method of extending the modulation bandwidth using an additional feedback loop around the VCO. The additional loop uses a delay-discriminator method of phase detection at a multiple of the reference frequency ( 𝑓ref ). Phase detection at a higher frequency ( 𝑓ref ) enables the bandwidth of the additional loop to be higher than the conventional PLL loop, which detects phase at the reference frequency. Because of the closed-loop operation, the modulation accuracy is preserved. The proposed method achieves a higher bandwidth than the wideband modulation method using digital pre-emphasis of the modulating signal. It is also significantly less sensitive to the VCO gain than the two-point modulation method that combines digital modulation of the feedback divider modulus and analog modulation at the VCO input. A prototype 2.4 GHz PLL with a 22.2 MHz reference in 0.13 𝜇𝑚 CMOS has a 3 dB modulation bandwidth of 600 kHz using the conventional in-loop modulation technique. The proposed method extends 3 dB bandwidth to 5 MHz. The prototype’s 22.5% bandwidth to reference frequency ratio is comparable to that of the two-point modulation technique. The thesis also investigates the use of the digital pre-emphasis method of increasing the effective bandwidth of PLL to speed up the step response of the PLL and thereby reduce the output frequency settling time whenever there is a change in the feedback divider modulus. PLL bandwidth is kept low for sufficient attenuation of spurious tones at multiples of the reference frequency. It also attenuates the noise from reference. The low bandwidth, however, results in a large setting time of the output frequency when the divider modulus is changed to switch to a new output frequency. The existing method of speeding up the transient involves dynamically changing the loop characteristic in one way or another. We present a technique for improving the settling time of an integer-N PLL by dynamically varying the division modulus. It is done by passing the frequency step control signal through a suitable pre-emphasis filter before applying it to the multi-modulus divider. Noise performance and stability remain unaffected since the main loop is not altered. Simulation of a third-order 1-GHz PLL with 10-MHz reference and 500-kHz bandwidth shows a 57% reduction in settling time. The settling time reduction is in the range of 45–75 % for ± 20 % variation in the component values. The constraint on the bandwidth of the PLL is for achieving sufficient attenuation of spurious tones and noise from the reference. These constraints can be overcome to a large extent by a better design or by consuming more power in the PLL. The thesis investigates another constraint on the PLL bandwidth that originates from the fundamental problem of PLL stability. This limitation can be observed if the PLL is analyzed in the discrete-time (DT) domain, which takes into consideration the phase sampling by the phase frequency detector (PFD) at the reference frequency. The commonly used continuous-time (CT) model of the PLL is a linear time-invariant (LTI) model independent of the reference frequency. If all poles and zeros of the loop are scaled by 𝛼 > 1, the loop stability remains unaffected, but the unity loop gain frequency fu scales by 𝛼. Hence, the CT model does not have any stability imposed limit on PLL bandwidth. In reality, PLL is a sampled system due to sampling of the divider output phase by the phase frequency detector (PFD) at every reference edge. Some blocks of the PLL are functionally nonlinear, which makes it a little complicated to analyze. With reasonable assumptions, a linear discrete-time (DT) model of PLL is developed using the impulse-invariance method. An expression for the discrete-time loop gain 𝐿(𝑧) is derived from the model. The location of closed-loop poles, which are zeros of 1 − 𝐿(𝑧), imposes an upper limit of 𝑓ref /𝜋 on the PLL bandwidth. The last section of the thesis analyzes the noise in a multi-stage divider chain and the impact of the relative sizing of different stages on the Figure-of-Merit (FoM) of the divider. The successive stage of a divider operates at a lower frequency and hence can afford more delay. Hence, it is reasonable to downscale them successively to save power. The analysis shows that it is not the optimum way of sizing from the noise point of view. We present a method to determine the scaling factor for different stages in a divider chain (ripple counter) to get the best jitter FoM(minimum of jitter times power product) for a given divider configuration. An analytic expression for the FoM normalized to the first stage of the divider chain is derived and then optimized to get the best jitter FoM. The analysis shows that scaling down the divider stages in proportion to their input frequency results in a very high jitter and a very poor jitter FoM. For a cascade of divide-by-M stages, each stage should be scaled up by √M compared to the previous stage. Circuit simulation results validate the analysis. When optimally sized, the FoM of a cascade of 8 divide-by-two stages is 14.7 dB better than scaling down the stages successively by a factor of two, which is the conventional method of sizing. Compared to 8 identical divide-by-two stages, optimal scaling has a 1.9 dB better FoM.

Event Details
Title: Wideband Modulation in a Phase-Locked Loop Using an Additional Feedback Around the VCO (PhD viva voce)
Date: July 01, 2026 at 03:00 PM
Venue: Google Meet (https://meet.google.com/ctq-pfud-urs)
Speaker: Mr. Sumit Kumar (EE10D047)
Guide: Dr. Nagendra Krishnapura
Type: PHD seminar