Biography

I am an Assistant Professor in the Integrated Circuits and Systems Group of the Department of Electrical Engineering, IIT Madras. I primarily work on Electronic Design Automation (EDA) Algorithms, specifically on automation of Back End of Line (BEOL) flow for custom digital, and analog/mixed-signal (AMS) designs.

Research Interests

  • Electronic Design Automation
  • Physical design
  • AMS and Custom-digital P&R
  • Mapping NP-hard/ complete problems to Ising machines

Personal Website

For more information, visit my personal website.

Recent Publications

Journals

  • S. Ramprasath, M. Madhusudan, A. K. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S. M. Burns, and S. S. Sapatnekar, “A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts,” ACM Transactions on Design Automation of Electronic Systems, March 2023.

Conference Proceedings

  • J. Poojary, S. Ramprasath, S. S. Sapatnekar, and R. Harjani, “Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN,” Proceedings of Radio Frequency Integrated Circuits Symposium (RFIC), 2023.
  • S. Ramprasath, A. K. Sharma, M. Madhusudan, S. Yaldiz, J. Poojary, R. Harjani, S. M. Burns, and S. S. Sapatnekar, “Analog/Mixed-Signal Layout Optimization using Optimal Well Taps,” Proceedings of the ACM International Symposium on Physical Design, 2022.
  • T. Dhar, S. Ramprasath, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S. S. Sapatnekar, “A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement,” Proceedings of Design, Automation and Test in Europe, 2022.

Patents

  • P. Yadav and S. Ramprasath, ” Keep-through regions for handling end-of-line rules in routing,” US 11,586,796 B1, Feb. 21, 2023.

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