Biography

  • I obtained my PhD degree in Electrical Engineering from IIT-Bombay in 1993, working with Prof. J.Vasi. My PhD work involved simulation of radiation effects in MOS transistors. Before enrolling for a PhD, I worked for a year in CDOT in their reliability and failure analysis group. Here I was involved in developing functional testers for various components ranging from photodiodes to microprocessors. I obtained my Masters degree in Electrical Engg. from RPI, Troy, NY in 1988 and a B.Tech degree in Engineering Physics from IIT-Bombay in 1986.
  • At IIT-Madras, I was initially involved in setting up the VLSI and FPGA laboratories. Here are photographs of the first couple of ICs from IITM (June 2002), designed by my PhD Student Sunil Rafeeque and fabricated through Europractice. They are 10-bit current steering DACs with circuits for built-in-self-test and reconfiguration.
  • Over the last few years, most of my work been in statistical timing, noise analysis and reduced order modelling.
  • My primary research interest is statistical and noise analysis of systems. Some of the areas I am working on are noise and jitter analysis of mixed signal systems, statistical timing and power analysis, approximate computing and reduced-order modelling.
  • If you are interested in doing an M.S./PhD in any of these areas and are also inclined to mathematics and programming, you can send me an email.

Research Interests

  • Approximate computing.
  • Statistical and noise analysis of systems.
  • Model order reduction.
  • Design optimization.

Personal Website

For more information, visit my personal website.

Recent Publications

  • K B N Girish, Nitin Chandrachoodan and Vinita Vasudevan, “ A smoothed LASSO based DNN Sparsification Technique”, IEEE Trans Circuits and Systems, 68-10, Oct 2021.
  • K B N Girish and V Vasudevan, “Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization IEEE Trans on Circuits and Systems 66-11(5): 848-852, 2019.
  • D Celia, Vinita Vasudevan and Nitin Chandrachoodan, “Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders”, IET Computers and Digital Techniques, vol 15, 2021, pp97-111.
  • D Celia, Vinita Vasudevan and Nitin Chandrachoodan, “Optimization of signal processing applications using parameterized error models for approximate adders”, ACM Trans Embedded Computing Systems, Vol 20, no 2, March 2021.
  • D Celia, Vinita Vasudevan and Nitin Chandrachoodan, “Optimizing power-accuracy trade-off in approximate adders”, Proc DATE, March 2018.
  • D Celia, Vinita Vasudevan and Nitin Chandrachoodan, “Probabilistic Error Modelling for two-part segmented Approximate Adders”, Proc ISCAS, May 2018.
  • V Charumathi, M Ramakrishna and V Vasudevan, “Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition.
  • V Vasudevan and M Ramakrishna, “An Efficient Algorithm for Frequency-Weighted Balanced Truncation of VLSI Interconnects in descriptor form”, Proc Des Automation Conf, 2015 (pdf).
  • Vinita Vasudevan and M Ramakrishna, “A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices”(2017).
  • P R Chithira and V Vasudevan,” Potential Critical Path Selection based on a Time-Varying Statistical Timing Analysis Framework”, IEEE Trans VLSI systems, vol 27, no 6, June 2019 (pdf).
  • P R Chithira and V Vasudevan, “A Hierarchical Technique for statistical path selection and critcality computation”, ACM Trans Des Automation of Electronic Systems (TODAES), vol 23, no 1, Oct 2017 (pdf).
  • S Ramprasath and V Vasudevan, “Efficient algorithms for discrete gate sizing and threshold voltage assignment based on an accurate analytical statistical yield gradient”, ACM Trans Des Automation of Elecronic Systems (TODAES), vol 21, no 4, May 2016.
  • S Ramprasath, M Vijaykumar and V Vasudevan, “A skew-normal canonical model for statistical static timing analysis”, IEEE Trans VLSI systems, vol 24(6), pp 2359-68, June 2016 (pdf).

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